(a) Field of the Invention
The present invention relates to a plasma display and a driving method thereof.
(b) Description of the Related Art
Recently, liquid crystal displays (LCDs), field emission displays (FEDs), and plasma displays have been actively developed. Among flat panel devices, plasma displays have better luminance and light emission efficiency as compared to the other types, and they also have wider view angles. Therefore, plasma displays have come into the spotlight as substitutes for conventional cathode ray tubes (CRTs) in large displays of greater than 40 inches.
A plasma display is a flat display that uses plasma generated via a gas discharge process to display characters or images, and tens to millions of pixels are provided thereon in a matrix format, depending on its size. Plasma displays are categorized into DC plasma displays and AC plasma displays, according to supplied driving voltage waveforms and discharge cell structures.
Since the DC plasma displays have electrodes exposed in the discharge space, they allow a current to flow in the discharge space while the voltage is supplied, and therefore they problematically require resistors for current restriction. On the other hand, since the AC plasma displays have electrodes covered by a dielectric layer, capacitances are naturally formed to restrict the current, and the electrodes are protected from ion shocks in the case of discharging. Accordingly, they have a longer lifespan than the DC plasma displays.
FIG. 1 shows a perspective view of an AC PDP, and FIG. 2 shows a cross-sectional view of the PDP of FIG. 1. An X electrode 3 and a Y electrode 4, disposed over a dielectric layer 14 and a protection film 15, are provided in parallel and form a pair with each other under a first glass substrate 11. The X and Y electrodes are made of transparent conductive material, and bus electrodes 6 made of metal are respectively formed on the surfaces of the X and Y electrodes 3 and 4.
A plurality of address electrodes 5 covered with a dielectric layer 14′ are installed on a second glass substrate 12. Barrier ribs 17 are formed in parallel with address electrodes 5, on dielectric layer 14′ in between address electrodes 5, and phosphor 18 is formed on the surface of dielectric layer 14′ and on both sides of barrier ribs 17. First and second glass substrates 11 and 12 having a discharge space 19 between them are provided facing each other so that Y electrode 4 and X electrode 3 may cross address electrode 5. Address electrode 5 and a discharge space 19 formed at a crossing part of Y electrode 4 and X electrode 3 form a discharge cell 20.
FIG. 3 shows a conventional plasma display electrode arrangement diagram. The plasma display electrode has an m×n matrix configuration, with address electrodes A1 to Am in a column direction, and Y electrodes Y1 to Yn and X electrodes X1 to Xn in a row direction, alternately. Discharge cell 20 shown in FIG. 3 corresponds to the discharge cell 20 shown in FIG. 1.
FIG. 4 shows a conventional plasma display driving waveform diagram. Each subfield includes a reset period, an address period, and a sustain discharge period. The reset period erases wall charge states of a previous sustain discharge, and sets up the wall charges in order to stably perform a next address. In the addressing period, the cells that are turned on and the cells that are not turned on in a panel are selected, and wall charges are accumulated to the cells that are turned on (i.e., the addressed cells). In the sustain discharge period, discharge for actually displaying pictures on the addressed cells is performed by alternately applying sustain discharge voltages to the X and Y electrodes.
The operation of the conventional plasma display driving method during the reset period will now be described in more detail. As shown in FIG. 4, the reset period includes an erase period, a Y ramp rising period, and a Y ramp falling period.
(1) Erase Period (I)
During this period, a falling ramp that gently falls from a sustain discharge voltage Vs to a ground potential (0V) is applied to the Y electrode while the X electrode is biased with a constant potential Vbias, thereby eliminating the wall charges formed in the previous sustain discharge period.
(2) Y Ramp Rising Period (II)
During this period, the address electrode and the X electrode are maintained at 0V, and a ramp voltage gradually rising from voltage Vs to voltage Vset is applied to the Y electrode. While the ramp voltage rises, weak resetting is generated to all the discharge cells from the Y electrode to the address electrode and the X electrode. As a result, the negative wall charges are accumulated to the Y electrode, and concurrently, the positive wall charges are accumulated to the address electrode and the X electrode.
(3) Y Ramp Falling Period (III)
In the latter part of the reset period, a ramp voltage that gradually falls from voltage Vs to the ground potential is applied to the Y electrode under the state that the X electrode maintains constant voltage Vbias. While the ramp voltage falls, weak resetting is generated again at all the discharge cells.
However, the sustain discharge operation is concurrently performed on all the discharge cells in the conventional plasma display after the address operation, from the first Y electrode to the last Y electrode, is complete. Therefore, since insufficient priming particles are generated in the discharge cells when a first sustain discharge pulse is applied after an address period in the conventional plasma display, bad discharge is generated.
Also, since the waveform applied to the Y electrode (to which waveforms for resetting and scanning are additionally applied) during the reset period is different from the waveform applied to the X electrode in the conventional plasma display, the circuit for driving the Y electrode is different from the circuit for driving the X electrode. Accordingly, no impedance matching on the driving circuits of the X and Y electrodes is performed, the waveforms alternately applied to the X and Y electrodes in the sustain discharge period are distorted, and bad discharges occur.